By Dirk Stroobandt
The roots of this ebook, and of the hot examine box that it defines, lie within the scaling of VLSI expertise. With gigahertz approach clocks and ever accelerating layout and strategy suggestions, interconnects became the restricting issue for either functionality and density. This expanding impression of interconnects at the approach implementation area necessitates new instruments and analytic options to help the approach fashion designer. With appreciate to modeling and research, the reaction to interconnect dom inance is evolutionary. Atomistic- and grain-level types of interconnect constitution, and function types at multi-gigahertz working frequencies, jointly advisor the choice of more advantageous fabrics and approach applied sciences (e. g. , damascene copper wires, low-permittivity dielectrics). formerly in major results (e. g. , mutual inductance) are extra into functionality mod els, as older approximations (e. g. , lumped-capacitance gate load types) are discarded. although, on the system-level and chip making plans point, the required reaction to interconnect dominance is progressive. Convergent layout flows don't require purely allotted RLC line types, repeater understanding, unifi cations with extraction and research, and so on. particularly, matters corresponding to wiring layer project, and early prediction of the source and function envelope for the method interconnect (in specific, in response to statistical versions of the procedure interconnect structure), additionally turn into severe. certainly, system-level interconnect prediction has emerged because the enabler of more advantageous interconnect modeling, less expensive approach architectures, and extra efficient layout technology.
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9 By linking those planes in free space, we can head for three-dimensional systems. 7LED: 'Light Emitting Diode' . 8VCSEL: 'Vertical Cavity Surface Emitting Laser' . 9Note that the possibility of routing in different layers alleviates routing problems but it does not fundamentally change the planar character of the entire structure. The end points of the interconnections still have to be connected to planar components in the same planar structure. Overview 21 Other possibilities for optical systems are linked with the interconnection pattern.
The area occupied by the chip has a profound impact on the price. Therefore, the algorithms must use all available space as much as possible. Moreover, the way the components are placed on the chip has an important influence on the chip performance. A more efficient layout requires good estimates of parameters such as the wire length after placement, the area used, the power dissipation, etc. These estimates help the designer to find a good layout. The most important conditions to obtain valuable designs are: • No wires with very high delay should exist.
The power dissipation should be minimal (low power). • The price for system design can not be too high. Chips should be cheap. All these conditions can be reduced to one very important one: the wires should be as short as possible. Wire length estimates are essential to be able to satisfy this condition. Three basic types of wire length estimates can be distinguished: a priori, a posteriori, and on line estimates [CK+98]. Overview 17 • A priori estimation seeks to estimate the total wire length of a layout design in advance, before the placement of the circuit in the physical architecture.
A Priori Wire Length Estimates for Digital Design by Dirk Stroobandt